1. Technical Field
The present invention relates to data processing systems and, more specifically, to input/output channel processing in such a system.
2. Description of the Related Art
Referring to FIG. 1, a block diagram representative of a prior art input/output (I/O) processor 50 is shown. The I/O processor 50 is of a type provided between a central processing unit ("CPU") and input/output devices in a large scale data processing system. The processor 50 consists of a channel manager 51 (in communication with the CPU), a channel processor 53 and a plurality of interface controllers 71-78.
Each of the plurality of interface controllers 71-78 is responsible for controlling the transmission of data in a plurality of I/O channels 60, for example, 16 channels. In one prior art embodiment, there are 8 interface controllers 71-78, each controlling 16 channels, for a total of 128 channels. Connection to any one of these channels may be had through a port 81 external to the data processing system.
Each of the interface controllers 71-78 contains a micro-code program for controlling data transmission in all of the channels in that controller. Essentially, each channel has an instruction pointer which points to its current micro-code instruction. A controller performs one micro-code instruction for one channel during a first clock cycle, increments the instruction pointer for that channel and then moves on to the next channel, performs one instruction for that channel and increments its' instruction pointer during the next clock cycle, and moves on to a subsequent channel in a subsequent clock cycle and repeats this process. All 16 channels in a controller 71-78 are processed in this sequential, time-sliced manner wherein one instruction per channel is performed per system clock cycle. Since there are 16 channels per controller, this means that an instruction for a particular channel is executed once every 16 system clock cycles.
Among the functions provided by each of the interface controllers is channel time-out monitoring. Time-out is an event known in the art and generally refers to a situation in which a signal has been transmitted and a response to the transmitted signal is due. If the response is not received within a predetermined amount of time, a time-out signal is issued indicating that the response has not timely come.
The time-out mechanism in an interface controller 71-78 is implemented by establishing a time-out period that is equal to a multiple of the system clock cycle time and decrementing (or incrementing) this period for a number of clock cycles equal to that multiple. For example, in a processor operating at 100 megahertz ("MHz"), the cycle time is 10 nanoseconds ("ns"). Since a decrement instruction for a specific channel would be executed one every 16 cycles, the decrement of one would be equal to 10 ns.times.16 or 160 ns. An established time-out period is then divided by 160 ns to determine the number of decrement instructions the processor of an interface controller must execute to arrive at a quantity equal to the time-out limit. For example, if the time-out limit is established to be 800 microseconds (".mu.s"), an interface controller will have to execute 5,000 decrement (or increment) instructions before a time-out occurs.
Given this large number of counting instructions, it is likely that a majority of processor time for each of the interface controllers 71-79 is spent executing a count operation, a relatively trivial operation for a processor.
Referring to the channel processor 53, the channel processor controls the allocation of all of the 128 input/output channels. Control signals are passed between each of the interface controllers 71-78 and channel processor 53. The channel processor functions, with respect to time-out, in a manner similar to that of the interface controllers 71-78. Instructions for each of the 128 channels are executed in a time sliced manner. Due to the aggregate number of channels, however, the channel processor 53 is effectively performing one instruction per channel every 128 cycles. This may be disadvantageously slow in some applications.
Furthermore, during normal operation of a data processing system, only a small number of channels are actually transmitting data at any given time. The channel processor 53 may be performing a time-out count for the vast majority of channels. Having a processor simply execute a count for, for example, 100 out of 128 channels is an inefficient use of the processor.